CPC H04R 19/04 (2013.01) [B81B 7/0058 (2013.01); B81B 7/0061 (2013.01); B81B 7/0064 (2013.01); B81B 2201/0257 (2013.01); B81B 2203/0127 (2013.01); B81B 2203/0315 (2013.01); B81B 2207/012 (2013.01); H04R 2201/003 (2013.01)] | 27 Claims |
1. A semiconductor wafer comprising a plurality of primary die portions, each primary die portion configured to define a primary die following dicing of the semiconductor wafer, wherein at least one primary die portion comprises a plurality of apertures, each aperture extending through the semiconductor wafer from an upper surface of the semiconductor wafer to a lower surface of the semiconductor wafer, wherein each aperture is suitable for receiving a respective secondary die.
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