US 11,736,594 B2
Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware
Dhaval Shah, Thane West (IN); Sunil Puranik, Pune (IN); Manoj Nambiar, Thane West (IN); Mahesh Damodar Barve, Pune (IN); Ishtiyaque Shaikh, Thane West (IN); Piyush Manavar, Thane West (IN); and Sharyu Vijay Mukhekar, Pune (IN)
Assigned to TATA CONSULTANCY SERVICES LIMITED, Mumbai (IN)
Filed by Tata Consultancy Services Limited, Mumbai (IN)
Filed on Jun. 16, 2021, as Appl. No. 17/349,085.
Claims priority of application No. IN202121007086 (IN), filed on Feb. 19, 2021.
Prior Publication US 2022/0311839 A1, Sep. 29, 2022
Int. Cl. G06F 15/173 (2006.01); H04L 69/16 (2022.01)
CPC H04L 69/16 (2013.01) 12 Claims
OG exemplary drawing
 
1. A Field Programmable Gate Array (FPGA) implemented method for a low-latency FPGA frame-work based on reliable User Datagram Protocol (UDP) and Transmission Control Protocol (TCP) re-assembly middleware:
receiving a plurality of data packets as input from a plurality clients, wherein the plurality of data packets are associated with a digitally configured task to be performed for the client by the FPGA and the plurality of data packets enables one of a TCP and a UDP, wherein each data packet within the plurality of data packets comprises a channel sequence number indicative of the client;
assembling the plurality of data packets based on the channel sequence number; identifying a missing channel sequence number in the assembled data packets based on a pre-defined sequence;
performing, based on the identification of the missing channel sequence number in the assembled data packets:
on identifying presence of the missing channel sequence number in the assembled data packets, requesting a re-transmission of the assembled data packets with the missing channel sequence number over a TCP channel based on a reliable UDP logic from the client to obtain a complete assembled data packets based on a TCP re-assembly logic, wherein the TCP re-assembly logic comprises converting the data packets into the complete assembled data packets at a pre-defined frequency based on a memory optimization implemented for a memory in a TCP First-In-First-Out (FIFO), wherein the memory includes a message writer memory, a data segment memory, and a descriptor memory,
wherein memory optimization implemented to the memory in a TCP re-assembly middleware architecture includes:
i. registering an output for a memory, wherein registering is implemented by utilizing a register and an input controller placed at the output of the memory, wherein registering the output for the memory enables implementation at the pre-defined frequency by:
a. holding a data for one clock to synchronize the data for one clock cycle;
b. the process of registering the output of memory for two clock, the FPGA is synthesized or implemented at the pre-defined frequency;
ii. slicing the memory based on a pre-defined slicing threshold to enable a FPGA implementation at the pre-defined frequency, wherein the slicing includes a horizontal slicing and a vertical slicing; and
on identifying absence of the missing channel sequence number in the assembled data packets, the assembled data packets to be retained as the complete assembled data packets;
extracting a plurality of relevant features from the complete assembled data packets using a domain knowledge base;
performing the digitally configured task using the plurality of relevant features from the complete assembled data packets; and
sharing the performed digitally configured task as an output to the client in response for the received data packets.