US 11,735,670 B2
Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors
Glenn A. Glass, Portland, OR (US); Anand S. Murthy, Portland, OR (US); Karthik Jambunathan, Krikland, WA (US); Cory C. Bomberger, Portland, OR (US); Tahir Ghani, Portland, OR (US); Jack T. Kavalieros, Portland, OR (US); Benjamin Chu-Kung, Boise, ID (US); Seung Hoon Sung, Portland, OR (US); and Siddharth Chouksey, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 8, 2021, as Appl. No. 17/497,864.
Application 17/497,864 is a continuation of application No. 16/649,716, granted, now 11,189,730, previously published as PCT/US2017/068414, filed on Dec. 26, 2017.
Prior Publication US 2022/0037530 A1, Feb. 3, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/161 (2006.01); H01L 27/088 (2006.01); H01L 29/775 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7851 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02546 (2013.01); H01L 21/02603 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/41733 (2013.01); H01L 29/41791 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/66522 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/78618 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
a nanostructure of semiconductor material including at least 70% germanium by atomic percentage;
a gate structure completely surrounding the nanostructure, the gate structure including a gate dielectric and a gate electrode;
a source region and a drain region both adjacent to the nanostructure such that the nanostructure is between the source and drain regions, the source region and the drain region comprising a semiconductor material comprising silicon, and at least one of the source region and the drain region including n-type impurity;
a contact structure on the at least one of the source region and the drain region; and
a layer of mono-crystalline semiconductor material distinct from and between the at least one of the source region and the drain region and the contact structure, the layer of mono-crystalline semiconductor material comprising the semiconductor material comprising silicon, and the mono-crystalline semiconductor material including the n-type impurity.