US 11,735,629 B2
Semiconductor devices and methods of manufacturing the same
Seung-Min Song, Hwaseong-si (KR); Woo-Seok Park, Ansan-si (KR); Jung-Gil Yang, Hwaseong-si (KR); Geum-Jong Bae, Suwon-si (KR); and Dong-Il Bae, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 3, 2021, as Appl. No. 17/541,625.
Application 17/541,625 is a continuation of application No. 16/996,334, filed on Aug. 18, 2020, granted, now 11,222,949.
Application 16/996,334 is a continuation of application No. 16/052,091, filed on Aug. 1, 2018, granted, now 10,784,344, issued on Sep. 22, 2020.
Claims priority of application No. 10-2017-0126077 (KR), filed on Sep. 28, 2017.
Prior Publication US 2022/0093735 A1, Mar. 24, 2022
Int. Cl. H01L 21/336 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/02 (2006.01); H01L 29/10 (2006.01); B82Y 10/00 (2011.01); H01L 29/786 (2006.01); H01L 29/775 (2006.01); H01L 29/40 (2006.01); H01L 21/3105 (2006.01); H01L 29/16 (2006.01); H01L 29/165 (2006.01); H01L 21/8234 (2006.01)
CPC H01L 29/0673 (2013.01) [B82Y 10/00 (2013.01); H01L 21/0262 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02636 (2013.01); H01L 21/3081 (2013.01); H01L 21/30604 (2013.01); H01L 27/0886 (2013.01); H01L 29/0653 (2013.01); H01L 29/0692 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66439 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 21/31053 (2013.01); H01L 21/823412 (2013.01); H01L 21/823425 (2013.01); H01L 27/088 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, the method comprising:
forming a fin structure on a substrate, the fin structure comprising sacrificial lines and semiconductor lines that are alternately and repeatedly stacked;
forming a dummy gate structure on the fin structure and the substrate, the dummy gate structure comprising a dummy gate insulation pattern and a dummy gate electrode that are sequentially stacked;
etching the fin structure using the dummy gate structure as an etching mask to expose an upper surface of the substrate;
etching sidewalls of the sacrificial lines to form a first recess;
etching a portion of the dummy gate insulation pattern exposed by the first recess to form a second recess;
forming a first spacer in the first and second recesses;
forming a source/drain layer on the upper surface of the substrate; and
replacing the dummy gate structure with a gate structure.