US 11,735,535 B2
Coaxial magnetic inductors with pre-fabricated ferrite cores
Kaladhar Radhakrishnan, Chandler, AZ (US); Krishna Bharath, Phoenix, AZ (US); and Clive Hendricks, Gilbert, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 8, 2019, as Appl. No. 16/596,328.
Prior Publication US 2021/0104475 A1, Apr. 8, 2021
Int. Cl. H01L 23/64 (2006.01); H01F 17/00 (2006.01); H01F 17/04 (2006.01); H01F 41/04 (2006.01); H01F 41/12 (2006.01); H01F 27/32 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/645 (2013.01) [H01F 17/0006 (2013.01); H01F 17/04 (2013.01); H01F 27/32 (2013.01); H01F 41/041 (2013.01); H01F 41/12 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01F 2017/0086 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19103 (2013.01)] 23 Claims
OG exemplary drawing
 
1. An inductor, comprising:
a plurality of plated-through-hole (PTH) vias in a substrate layer;
a plurality of magnetic interconnects with a plurality of openings in the substrate layer, wherein the plurality of openings of the plurality of magnetic interconnects surround the plurality of PTH vias;
an insulating layer in the substrate layer, wherein the insulating layer laterally surrounds and is in contact with an outermost surface of the plurality of magnetic interconnects;
a first conductive layer over the plurality of PTH vias, the plurality of magnetic interconnects, and the insulating layer; and
a second conductive layer below the plurality of PTH vias, the plurality of magnetic interconnects, and the insulating layer.