US 11,735,531 B2
Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
Srinivas V. Pietambaram, Gilbert, AZ (US); Sri Ranga Sai Boyapati, Chandler, AZ (US); Robert A. May, Chandler, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); Javier Soto Gonzalez, Chandler, AZ (US); and Kwangmo Lim, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 13, 2021, as Appl. No. 17/374,886.
Application 17/374,886 is a continuation of application No. 16/326,679, granted, now 11,101,222, previously published as PCT/US2016/054559, filed on Sep. 29, 2016.
Prior Publication US 2021/0343653 A1, Nov. 4, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 23/00 (2013.01); H01L 24/06 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/18 (2013.01); H01L 2224/24137 (2013.01); H01L 2924/18162 (2013.01)] 5 Claims
OG exemplary drawing
 
1. A device, comprising:
a first die having a first plurality of die pads;
a second die having a second plurality of die pads;
a molding layer laterally around the first die and the second die and between the first die and the second die, the molding layer laterally around the first plurality of die pads and the second plurality of die pads, wherein the molding layer has a top surface co-planar with a top surface of the first plurality of die pads and with a top surface of the second plurality of die pads;
a plurality of conductive vias directly on and in contact with the first plurality of die pads and the second plurality of die pads; and
a plurality of conductive lines directly on and in contact with the top surface of the molding layer.