CPC H01L 21/8221 (2013.01) [H01L 21/823871 (2013.01); H01L 21/823885 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H10B 69/00 (2023.02); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01)] | 19 Claims |
1. An assembly comprising a CMOS tier, the CMOS tier comprising:
a PMOS deck comprising a plurality of p-channel transistors which are substantially identical to one another;
an NMOS deck comprising a plurality of n-channel transistors which are substantially identical to one another; the NMOS deck being vertically offset relative to the PMOS deck;
an insulative region between the PMOS deck and the NMOS deck; and
a vertically extending post in direct physical contact with a first source/drain region of an n-channel transistor in the NMOS deck and in direct physical contact with a second source/drain region of a p-channel transistor in the PMOS deck.
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