US 11,735,479 B2
Assemblies containing PMOS decks vertically-integrated with NMOS decks, and methods of forming integrated assemblies
Scott E. Sills, Boise, ID (US); and Kurt D. Beigel, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,856.
Application 16/402,570 is a division of application No. 15/857,974, filed on Dec. 29, 2017, granted, now 10,410,925, issued on Sep. 10, 2019.
Application 17/532,856 is a continuation of application No. 16/402,570, filed on May 3, 2019, granted, now 11,211,292.
Prior Publication US 2022/0077000 A1, Mar. 10, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/12 (2006.01); H01L 21/822 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 27/092 (2006.01); H01L 23/522 (2006.01); H01L 27/06 (2006.01); H10B 69/00 (2023.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/8221 (2013.01) [H01L 21/823871 (2013.01); H01L 21/823885 (2013.01); H01L 21/84 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/0688 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H10B 69/00 (2023.02); H01L 29/7827 (2013.01); H01L 29/78642 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An assembly comprising a CMOS tier, the CMOS tier comprising:
a PMOS deck comprising a plurality of p-channel transistors which are substantially identical to one another;
an NMOS deck comprising a plurality of n-channel transistors which are substantially identical to one another; the NMOS deck being vertically offset relative to the PMOS deck;
an insulative region between the PMOS deck and the NMOS deck; and
a vertically extending post in direct physical contact with a first source/drain region of an n-channel transistor in the NMOS deck and in direct physical contact with a second source/drain region of a p-channel transistor in the PMOS deck.