US 11,735,460 B2
Integrated circuit devices with an engineered substrate
Vladimir Odnoblyudov, Danville, CA (US); Dilip Risbud, San Jose, CA (US); Ozgur Aktas, Pleasanton, CA (US); and Cem Basceri, Los Gatos, CA (US)
Assigned to Qromis, Inc., Santa Clara, CA (US)
Filed by QROMIS, Inc., Santa Clara, CA (US)
Filed on Jul. 28, 2021, as Appl. No. 17/387,861.
Application 16/704,894 is a division of application No. 16/213,512, filed on Dec. 7, 2018, granted, now 10,535,547, issued on Jan. 14, 2020.
Application 16/213,512 is a division of application No. 15/684,753, filed on Aug. 23, 2017, granted, now 10,181,419, issued on Jan. 15, 2019.
Application 17/387,861 is a continuation of application No. 16/704,894, filed on Dec. 5, 2019, granted, now 11,107,720.
Claims priority of provisional application 62/378,382, filed on Aug. 23, 2016.
Prior Publication US 2021/0358795 A1, Nov. 18, 2021
Int. Cl. H01L 29/778 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01); H01L 29/861 (2006.01); H01L 21/285 (2006.01); H01L 21/18 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/48 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); C30B 25/18 (2006.01); C30B 29/06 (2006.01); C30B 29/40 (2006.01); H01L 29/872 (2006.01); H01L 29/40 (2006.01)
CPC H01L 21/6835 (2013.01) [C30B 25/183 (2013.01); C30B 29/06 (2013.01); C30B 29/406 (2013.01); H01L 21/0242 (2013.01); H01L 21/0254 (2013.01); H01L 21/0257 (2013.01); H01L 21/02428 (2013.01); H01L 21/02458 (2013.01); H01L 21/18 (2013.01); H01L 21/28264 (2013.01); H01L 21/28587 (2013.01); H01L 21/4807 (2013.01); H01L 21/762 (2013.01); H01L 29/1033 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/4175 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/66143 (2013.01); H01L 29/66204 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01); H01L 29/7787 (2013.01); H01L 29/861 (2013.01); H01L 29/8613 (2013.01); H01L 29/872 (2013.01); H01L 29/1066 (2013.01); H01L 29/402 (2013.01); H01L 2221/6835 (2013.01); H01L 2221/68345 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device comprising:
a substrate comprising:
a polycrystalline ceramic core;
a first adhesion layer coupled to the polycrystalline ceramic core;
a barrier layer coupled to the first adhesion layer;
a bonding layer coupled to the barrier layer; and
a substantially single crystal layer coupled to the bonding layer;
a buffer layer coupled to the substantially single crystal layer, the buffer layer comprising a first portion and a second portion adjacent to the first portion; and
a plurality of semiconductor devices coupled to the buffer layer.