CPC G11C 29/4401 (2013.01) [G11C 5/04 (2013.01); G11C 11/401 (2013.01); G11C 29/022 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); G11C 29/783 (2013.01); G11C 29/88 (2013.01); G11C 2029/4402 (2013.01)] | 20 Claims |
1. A command/address (C/A) buffer integrated circuit (IC) chip, comprising:
a primary C/A interface for coupling to a memory controller, the primary C/A interface to receive command and address information from the memory controller for a given data transfer operation;
a secondary C/A interface for coupling to at least one memory device;
repair circuitry to monitor the address information to detect a data transfer operation associated with known failure storage locations, the repair circuitry to generate a substitute address for a given known failure storage location associated with the data transfer operation; and
a communications interface to communicate the substitute address to at least one data buffer IC chip.
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