US 11,735,255 B2
Voltage equalization for pillars of a memory array
Corrado Villa, Sovico (IT); Ferdinando Bedeschi, Biassono (IT); and Paolo Fantini, Vimercate (IT)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 4, 2022, as Appl. No. 17/880,804.
Application 17/880,804 is a continuation of application No. 17/116,893, filed on Dec. 9, 2020, granted, now 11,437,097.
Prior Publication US 2022/0392527 A1, Dec. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 13/00 (2006.01); H10N 70/00 (2023.01); H10N 70/20 (2023.01)
CPC G11C 13/0026 (2013.01) [G11C 13/00 (2013.01); G11C 13/003 (2013.01); G11C 13/0004 (2013.01); H10N 70/066 (2023.02); H10N 70/231 (2023.02); H10N 70/882 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a plurality of conductive pillars over a substrate of a memory die;
a respective set of memory cells, of a plurality of memory cells, along each conductive pillar of the plurality of conductive pillars, each memory cell of the respective set of memory cells coupled with the conductive pillar and coupled with a respective access line of a plurality of access lines; and
a material in contact with the plurality of conductive pillars and configured to dissipate a voltage difference between each conductive pillar of the plurality of conductive pillars and a voltage source.