US 11,735,247 B2
Semiconductor device with word line degradation monitor and associated methods and systems
Gitanjali T. Ghosh, Boise, ID (US); Debra M. Bell, Boise, ID (US); Arunmozhi R. Subramaniam, Boise, ID (US); Roya Baghi, Boise, ID (US); Deepika Thumsi Umesh, Boise, ID (US); and Sue-Fern Ng, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 15, 2022, as Appl. No. 17/672,537.
Application 17/672,537 is a continuation of application No. 17/022,030, filed on Sep. 15, 2020, granted, now 11,270,757.
Claims priority of provisional application 62/955,822, filed on Dec. 31, 2019.
Prior Publication US 2022/0172768 A1, Jun. 2, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/408 (2006.01); G11C 11/4099 (2006.01); G11C 11/4076 (2006.01); G11C 11/4074 (2006.01)
CPC G11C 11/4085 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4099 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array including a memory bank having a plurality of word lines;
a comparison circuit coupled with the memory array and configured to:
detect a first signal from the memory bank, wherein the first signal is associated with a command executed at a word line of the plurality;
detect a first transition in the first signal and a second transition in a reference signal;
determine that the first transition occurs after the second transition; and
notify a host device of the determination.