CPC G11C 11/4085 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4076 (2013.01); G11C 11/4099 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory array including a memory bank having a plurality of word lines;
a comparison circuit coupled with the memory array and configured to:
detect a first signal from the memory bank, wherein the first signal is associated with a command executed at a word line of the plurality;
detect a first transition in the first signal and a second transition in a reference signal;
determine that the first transition occurs after the second transition; and
notify a host device of the determination.
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