CPC G11B 5/59616 (2013.01) [G11B 5/012 (2013.01)] | 20 Claims |
1. An apparatus comprising:
an integrated circuit including:
a detector circuit configured to detect a bit sequence read from a patterned medium;
a data generator circuit coupled to a delay line and configured to generate bits of a known data pattern;
multiple bit-error counters coupled to the delay line and each configured to compare a bit or shifted bit of the known data pattern to a bit of the detected bit sequence and count a number of bit-errors over a period of time;
a control circuit configured to count a number of bits processed by the bit-error counters;
multiple registers, each of the multiple registers configured to store a result of a corresponding bit-error counter over the period of time; and
an adjustment circuit configured to modify a count of grain patterns between two servo wedges of the patterned medium based on the results of the bit-error counters stored in the registers, the adjustment circuit further configured to store the modified count of grain patterns to enable synchronous writing of the patterned medium.
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