US 11,735,119 B2
Shift register unit, gate driving circuit and control method thereof and display apparatus
Zhidong Yuan, Beijing (CN); Yongqian Li, Beijing (CN); and Can Yuan, Beijing (CN)
Assigned to HEFEI BOE JOINT TECHNOLOGY CO., LTD., Anhul (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by Hefei BOE Joint Technology Co., Ltd., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on May 23, 2022, as Appl. No. 17/750,804.
Application 17/750,804 is a continuation of application No. 16/964,712, granted, now 11,355,070, previously published as PCT/CN2020/070210, filed on Jan. 3, 2020.
Claims priority of application No. 201910159457.X (CN), filed on Mar. 1, 2019.
Prior Publication US 2022/0284863 A1, Sep. 8, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/32 (2016.01); G09G 3/3266 (2016.01); G11C 19/28 (2006.01); G09G 3/3233 (2016.01)
CPC G09G 3/3266 (2013.01) [G11C 19/28 (2013.01); G09G 3/3233 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01); G09G 2310/08 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A shift register unit, comprising:
a first shift register coupled to an input signal terminal, a first clock signal terminal and a second clock signal terminal, and configured to generate a first output signal based on a signal at the first clock signal terminal and generate a second output signal based on a signal at the second clock signal terminal under a control of a signal at the input signal terminal; and
a second shift register coupled to the input signal terminal and a third clock signal terminal, and configured to generate a third output signal based on a signal at the third clock signal terminal under the control of the signal at the input signal terminal;
wherein the first shift register comprises:
a first control circuit coupled to the input signal terminal and a reset signal terminal, and configured to control a potential at a pull-up node of the first shift register and a potential at a pull-down node of the first shift register according to a signal at the input signal terminal and a signal at the reset signal terminal;
a first output circuit coupled to the first clock signal terminal, the pull-up node of the first shift register, and the pull-down node of the first shift register, and configured to generate the first output signal based on the signal at the first clock signal terminal under a control of the potential at the pull-up node of the first shift register and the potential at the pull-down node of the first shift register; and
a second output circuit coupled to the second clock signal terminal, the pull-up node of the first shift register, and the pull-down node of the first shift register, and configured to generate the second output signal based on a signal at the second clock signal terminal under the control of the potential at the pull-up node of the first shift register and the potential at the pull-down node of the first shift register.