US 11,734,482 B1
Visual representation to assess quality of input stimulus in transistor-level circuits
Mayukh Bhattacharya, Palo Alto, CA (US); Aleksandrs Krjukovs, San Jose, CA (US); and Chih-Ping Antony Fan, Saratoga, CA (US)
Assigned to Synopsys, Inc., Mountain View, CA (US)
Filed by Synopsys, Inc., Mountain View, CA (US)
Filed on Nov. 9, 2021, as Appl. No. 17/522,566.
Claims priority of provisional application 63/111,507, filed on Nov. 9, 2020.
Int. Cl. G06F 30/3308 (2020.01); G06F 30/343 (2020.01); G06F 30/347 (2020.01)
CPC G06F 30/343 (2020.01) [G06F 30/3308 (2020.01); G06F 30/347 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
accessing a transistor-level circuit simulation of a circuit's response to an input stimulus, the circuit comprising a plurality of transistors;
determining activity levels for the transistors in the circuit from the transistor-level circuit simulation; and
rendering, by a processor, a graphical representation of the circuit, wherein the graphical representation comprises:
graphical elements that represent components of the circuit, wherein the graphical elements are color coded according to the activity levels of the transistors in the corresponding components; and
at least one of sparkline graphs showing the activity levels of the components and sparkline graphs showing nodal voltages of the components.