US 11,734,406 B2
Secure tamper resistant smart card
Hock Thye Law, Oceanside, CA (US); Orang Dialameh, Topanga, CA (US); Ulrich Franz Buddemeier, Venice, CA (US); Lyn Phuong Nguyen, San Diego, CA (US); Lun Feng Tan, Vista, CA (US); Alexandre Charapov, San Diego, CA (US); Tim Dorcey, Santa Monica, CA (US); and Imraan Ahmed, San Diego, CA (US)
Assigned to ETHERNOM, INC., Oceanside, CA (US)
Filed by ETHERNOM, INC., Oceanside, CA (US)
Filed on Jan. 20, 2022, as Appl. No. 17/580,387.
Application 17/580,387 is a continuation of application No. 16/352,657, filed on Mar. 13, 2019, granted, now 11,301,554.
Claims priority of provisional application 62/728,016, filed on Sep. 6, 2018.
Claims priority of provisional application 62/642,548, filed on Mar. 13, 2018.
Prior Publication US 2022/0147974 A1, May 12, 2022
Int. Cl. G06F 21/00 (2013.01); G06F 21/34 (2013.01); G06F 21/32 (2013.01); G06Q 20/34 (2012.01); G06Q 20/40 (2012.01); H04L 9/14 (2006.01); H04L 9/32 (2006.01); G06N 7/01 (2023.01)
CPC G06F 21/34 (2013.01) [G06F 21/32 (2013.01); G06N 7/01 (2023.01); G06Q 20/341 (2013.01); G06Q 20/40145 (2013.01); H04L 9/14 (2013.01); H04L 9/3231 (2013.01); H04L 9/3247 (2013.01); H04L 2209/12 (2013.01); H04L 2209/80 (2013.01)] 34 Claims
OG exemplary drawing
 
1. A smart card comprising:
a plurality of dedicated hardware circuit blocks electrically coupled via a bus interconnection, the plurality of dedicated hardware circuit blocks comprising:
an identification input circuitry configured to capture user credentials from an interaction by a user with the smart card;
memory circuitry configured to store an identification template corresponding to one or more registered users of the smart card;
user identification circuitry coupled to the memory and electrically coupled to the identification input circuitry, the identification circuitry configured to authenticate that user credentials received from the identification input circuitry correspond to the one or more registered users; and
a microcontroller comprising one or more processors and configured to schedule set up and execution of the dedicated hardware blocks;
wherein the user credentials comprise an image and wherein the user identification circuitry comprises (i) an image enhancement block configured to perform image processing on the image, (ii) a minutiae detection block configured to detect minutiae of the image, and (iii) a comparison block configured to compare the image against the identification template retrieved from the memory circuit;
wherein each of the image enhancement block, minutiae detection block, and comparison block is one of the plurality of dedicated hardware circuit blocks, and configured for reduced data bit widths based on sequential and parallel processing.