CPC G06F 21/34 (2013.01) [G06F 21/32 (2013.01); G06N 7/01 (2023.01); G06Q 20/341 (2013.01); G06Q 20/40145 (2013.01); H04L 9/14 (2013.01); H04L 9/3231 (2013.01); H04L 9/3247 (2013.01); H04L 2209/12 (2013.01); H04L 2209/80 (2013.01)] | 34 Claims |
1. A smart card comprising:
a plurality of dedicated hardware circuit blocks electrically coupled via a bus interconnection, the plurality of dedicated hardware circuit blocks comprising:
an identification input circuitry configured to capture user credentials from an interaction by a user with the smart card;
memory circuitry configured to store an identification template corresponding to one or more registered users of the smart card;
user identification circuitry coupled to the memory and electrically coupled to the identification input circuitry, the identification circuitry configured to authenticate that user credentials received from the identification input circuitry correspond to the one or more registered users; and
a microcontroller comprising one or more processors and configured to schedule set up and execution of the dedicated hardware blocks;
wherein the user credentials comprise an image and wherein the user identification circuitry comprises (i) an image enhancement block configured to perform image processing on the image, (ii) a minutiae detection block configured to detect minutiae of the image, and (iii) a comparison block configured to compare the image against the identification template retrieved from the memory circuit;
wherein each of the image enhancement block, minutiae detection block, and comparison block is one of the plurality of dedicated hardware circuit blocks, and configured for reduced data bit widths based on sequential and parallel processing.
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