US 11,734,173 B2
Memory access bounds checking for a programmable atomic operator
Tony Brewer, Plano, TX (US); Dean E. Walker, Allen, TX (US); and Chris Baronne, Allen, TX (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 30, 2022, as Appl. No. 17/854,770.
Application 17/854,770 is a continuation of application No. 17/075,073, filed on Oct. 20, 2020, granted, now 11,379,365.
Prior Publication US 2022/0414004 A1, Dec. 29, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/00 (2006.01); G06F 12/06 (2006.01); G06F 12/02 (2006.01); G06F 12/0844 (2016.01)
CPC G06F 12/0607 (2013.01) [G06F 12/0223 (2013.01); G06F 12/0844 (2013.01); G06F 2212/1012 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an interface to connect the apparatus to a memory when in operation; and
processing circuitry that, when in operation, is configured to:
determine that a memory request from an executing program is outside a contiguous memory address range in a memory, the contiguous memory address range defined by a base memory address for the program and an interleave size; and
refuse execution of the memory request based on the memory request being outside the contiguous memory address range in the memory.