US 11,733,884 B2
Managing storage reduction and reuse with failing multi-level memory cells
Luca Bert, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 19, 2021, as Appl. No. 17/207,548.
Prior Publication US 2022/0300175 A1, Sep. 22, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0626 (2013.01) [G06F 3/0655 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
receiving, by a host system, an indication that a storage capacity of a memory sub-system is affected by a failure, wherein the memory sub-system stores data of a storage structure and comprises memory cells storing multiple bits per cell;
instructing, by the host system, the memory sub-system to operate at a reduced capacity, wherein the reduced capacity reduces quantity of bits stored per memory cell;
receiving, by the host system, an indication that the memory sub-system comprises data in excess of the reduced capacity;
providing, by the host system, a storage location to the memory sub-system, wherein the storage location is external to the memory sub-system; and
enabling the memory sub-system to store the data of the storage structure at the storage location.