CPC G01R 31/3187 (2013.01) [G01R 31/31704 (2013.01); G01R 31/318511 (2013.01); G01R 31/318513 (2013.01)] | 21 Claims |
1. An electronic assembly having built-in self-test of chiplets assembled in a heterogeneous process, the assembly comprising:
a host wafer having a first circuit including a plurality M of wafer transistors and a plurality of wafer passive, non-transistor devices;
a plurality of chiplets having a second circuit including at least one Y radio frequency (RF) chiplet transistor;
electrical interconnects between the chiplets and wafer, wherein the electrical interconnects electrically connect the first circuit to the second circuit; and
a plurality of oscillators each having some X of the plurality M of wafer transistors, the at least one Y radio frequency (RF) chiplet transistor of a chiplet and some of the electrical interconnects, wherein each oscillator of the plurality of oscillators produces a signal for the built-in self-test circuit for testing an assembly design of the electronic assembly and a speed of the at least one Y radio frequency (RF) chiplet transistor of the chiplet.
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