CPC A47K 11/02 (2013.01) [E04H 1/1216 (2013.01); E04H 15/38 (2013.01); G06F 13/4022 (2013.01); Y02A 50/30 (2018.01)] | 18 Claims |
1. A system on a chip (SoC), comprising:
a first data processing engine in an array of data processing engines;
a second data processing engine in the array of data processing engines; and
an interconnect configured to transmit streaming data between the first and second data processing engines, wherein the interconnect comprises a plurality of streaming interconnects comprising ports that are selectively configurable into a circuit switching mode and a packet switching mode,
wherein, when configured in the circuit switching mode, the streaming data routed through the ports is deterministic and the streaming data comprises a plurality of packets, each comprising a respective header, wherein the respective header comprises a stream ID assigning a corresponding packet to a logical stream, wherein a first streaming interconnect of the plurality of streaming interconnects comprises a first slave port, a second slave port, and a master port that are configured in the packet switching mode, wherein the first slave port transmits a first packet with a first value of the stream ID to the master port and the second slave port transmits a second packet with a second value of the stream ID to the master port, wherein the first and second packets are assigned to different logical streams,
wherein, when configured in the packet switching mode, streaming data routed through the ports is non-deterministic.
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