US 11,730,069 B2
Memory cell structures
Scott E. Sills, Boise, ID (US); and D. V. Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 13, 2020, as Appl. No. 16/926,837.
Application 16/926,837 is a division of application No. 15/423,965, filed on Feb. 3, 2017, granted, now 10,734,581.
Application 15/423,965 is a continuation of application No. 13/899,919, filed on May 22, 2013, granted, now 9,691,981, issued on Jun. 27, 2017.
Prior Publication US 2020/0343449 A1, Oct. 29, 2020
Int. Cl. H10N 70/00 (2023.01); H10B 63/00 (2023.01)
CPC H10N 70/066 (2023.02) [H10B 63/20 (2023.02); H10B 63/22 (2023.02); H10B 63/82 (2023.02); H10B 63/84 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A memory cell, comprising:
a plurality of stack structures in a length direction parallel to one another, and separated from each other in a first direction perpendicular to the length direction, wherein each of the plurality of stack structures comprises;
plural select device stacks; and
a dielectric material comprising plural segments;
an electrode material formed in plural segments, each electrode segment extending in the length direction; and
a non-conformal encapsulating material encapsulating the electrode material, such that there is encapsulating material on an entire top surface of the memory cell and on side surfaces of the memory cell,
wherein the top surface comprises a programmable material, and the side surfaces comprise the first electrode, the second electrode, and the select device, and
wherein more of the encapsulating material is on a top surface of the memory cell than on the side surfaces of the memory cell.