US 11,730,066 B2
Systems and methods for superconducting devices used in superconducting circuits and scalable computing
Mark W. Johnson, Vancouver (CA); Paul I. Bunyk, New Westminster (CA); Andrew J. Berkley, Vancouver (CA); Richard G. Harris, North Vancouver (CA); Kelly T. R. Boothby, Burnaby (CA); Loren J. Swenson, San Jose, CA (US); Emile M. Hoskinson, Vancouver (CA); Christopher B. Rich, Vancouver (CA); and Jan E. S. Johansson, Kristiansand (NO)
Assigned to 1372934 B.C. LTD., Burnaby (CA)
Filed by D-WAVE SYSTEMS INC., Burnaby (CA)
Filed on Aug. 11, 2021, as Appl. No. 17/399,375.
Application 17/399,375 is a continuation of application No. 16/098,801, granted, now 11,127,893, previously published as PCT/US2017/030857, filed on May 3, 2017.
Claims priority of provisional application 62/405,027, filed on Oct. 6, 2016.
Claims priority of provisional application 62/331,287, filed on May 3, 2016.
Prior Publication US 2023/0143506 A1, May 11, 2023
Int. Cl. H10N 60/12 (2023.01); G06N 10/00 (2022.01); H10N 60/80 (2023.01)
CPC H10N 60/124 (2023.02) [G06N 10/00 (2019.01); H10N 60/805 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A quantum processor comprising:
a plurality of programmable devices comprising superconducting qubits and one or more couplers communicatively coupling the superconducting qubits; and
a first digital-analog converter (DAC) operable to drive a current in a target device of the plurality of programmable devices, the first DAC coupleable to the target device and comprising:
a first superconducting loop, in operation the first superconducting loop having a first charge carrier density; and
a first energy storage element interrupting the first superconducting loop, in operation the first energy storage element having a second charge carrier density less than the first charge carrier density, thereby providing a first kinetic inductance.