CPC H10N 60/124 (2023.02) [G06N 10/00 (2019.01); H10N 60/805 (2023.02)] | 20 Claims |
1. A quantum processor comprising:
a plurality of programmable devices comprising superconducting qubits and one or more couplers communicatively coupling the superconducting qubits; and
a first digital-analog converter (DAC) operable to drive a current in a target device of the plurality of programmable devices, the first DAC coupleable to the target device and comprising:
a first superconducting loop, in operation the first superconducting loop having a first charge carrier density; and
a first energy storage element interrupting the first superconducting loop, in operation the first energy storage element having a second charge carrier density less than the first charge carrier density, thereby providing a first kinetic inductance.
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