US 11,730,015 B2
Display device
Sang Jin Jeon, Hwaseong-si (KR); Cheol-Gon Lee, Suwon-si (KR); and Sang-Uk Lim, Hwaseong-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-si (KR)
Filed by Samsung Display Co., Ltd., Yongin-si (KR)
Filed on Nov. 20, 2020, as Appl. No. 17/100,160.
Application 17/100,160 is a continuation of application No. 16/398,193, filed on Apr. 29, 2019, granted, now 10,847,595.
Claims priority of application No. 10-2018-0072568 (KR), filed on Jun. 25, 2018.
Prior Publication US 2021/0074786 A1, Mar. 11, 2021
Int. Cl. H10K 59/121 (2023.01); G09G 3/3225 (2016.01); H10K 59/126 (2023.01); H10K 59/131 (2023.01); H01L 27/12 (2006.01)
CPC H10K 59/1216 (2023.02) [G09G 3/3225 (2013.01); H10K 59/126 (2023.02); H10K 59/1213 (2023.02); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2320/0233 (2013.01); G09G 2320/0242 (2013.01); H01L 27/1255 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A display device comprising:
a substrate;
a first transistor disposed on the substrate, the first transistor including a channel region, a gate electrode, a first electrode electrically connected to a driving voltage line, and a second electrode;
a second transistor including a gate electrode, a first electrode electrically connected to the second electrode of the first transistor, and a second electrode electrically connected to the gate electrode of the first transistor;
a third transistor including a gate electrode electrically connected to a first scan line, a first electrode electrically connected to a data line, and a second electrode electrically connected to a first node;
a fifth transistor including a gate electrode electrically connected to a second scan line, a first electrode electrically connected to the first node, and a second electrode electrically connected to the driving voltage line;
a first capacitor including a first terminal electrically connected to the first node, and a second terminal electrically connected to the driving voltage line; and
a second capacitor including a first terminal electrically connected to the gate electrode of the first transistor, and a second terminal electrically connected to the first node,
wherein the first capacitor and the second capacitor overlap the first transistor in a plan view, and
the first capacitor and the second capacitor overlap each other over the first transistor in the plan view.