US 11,730,000 B2
3-dimensional nor string arrays in segmented stacks
Eli Harari, Saratoga, CA (US); and Wu-Yi Chien, San Jose, CA (US)
Assigned to SunRise Memory Corporation, San Jose, CA (US)
Filed by Sunrise Memory Corporation, San Jose, CA (US)
Filed on Oct. 4, 2021, as Appl. No. 17/493,502.
Application 17/493,502 is a continuation of application No. 16/859,960, filed on Apr. 27, 2020, granted, now 11,180,861.
Application 16/859,960 is a continuation of application No. 16/006,573, filed on Jun. 12, 2018, granted, now 10,692,874, issued on Jun. 23, 2020.
Claims priority of provisional application 62/522,661, filed on Jun. 20, 2017.
Prior Publication US 2022/0025532 A1, Jan. 27, 2022
Int. Cl. H10B 69/00 (2023.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 43/00 (2023.01); H10B 43/20 (2023.01); H10B 43/30 (2023.01); G11C 16/04 (2006.01); C25B 11/051 (2021.01); C25B 3/25 (2021.01); C25B 11/075 (2021.01); B01J 37/16 (2006.01); C01G 3/00 (2006.01); C07C 1/12 (2006.01); C22B 15/00 (2006.01); C30B 7/14 (2006.01); C30B 29/02 (2006.01); C30B 29/64 (2006.01)
CPC H10B 69/00 (2023.02) [B01J 37/16 (2013.01); C01G 3/00 (2013.01); C07C 1/12 (2013.01); C22B 15/00 (2013.01); C25B 3/25 (2021.01); C25B 11/051 (2021.01); C25B 11/075 (2021.01); C30B 7/14 (2013.01); C30B 29/02 (2013.01); C30B 29/64 (2013.01); G11C 16/04 (2013.01); H01L 23/528 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 43/00 (2023.02); H10B 43/20 (2023.02); H10B 43/30 (2023.02); C07C 2523/72 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A process for forming a memory structure, comprising:
providing a semiconductor substrate having a planar surface;
forming a first memory module above the planar surface, such that the first memory module includes a 3-dimensional array of NOR-type memory strings that comprises a plurality of NOR-type memory strings, with (i) two or more of the NOR-type memory strings being separated from each other along a first direction that is substantially parallel the planar surface and two or more of the NOR-type memory strings being separated from each other along a second direction that is orthogonal to the first direction and substantially perpendicular the planar surface, (ii) each of the NOR-type memory strings comprising a plurality of thin-film storage transistors, and (iii) a set of local word line conductors, each running along the second direction to serve as gate electrodes to the thin-film storage transistors of one or more of the NOR-type memory strings;
forming a first set of global conductors, such that the global conductors are (i) spaced from each other along a third direction that is substantially orthogonal both the first and second directions and (ii) each running along the first direction, in direct contact with selected local word line conductors of the first memory module;
forming a second memory module above the first memory module and the first set of global conductors, such that the second memory module also includes a 3-dimensional array of NOR-type memory strings that comprises a plurality of NOR-type memory strings, with (i) two or more of the NOR-type memory strings being separated from each other along the first direction and two or more of the NOR-type memory strings being separated from each other along the second direction, (ii) each of the NOR-type memory strings comprising a plurality of thin-film storage transistors, and (iii) a set of local word line conductors, each running along the second direction to serve as gate electrodes to the thin-film storage transistors of one or more of the NOR-type memory strings, and such that the first set of global conductors are also each in direct contact with selected local word line conductors of the second memory module.