US 11,729,998 B2
Semiconductor memory device having a variable resistence layer
Jae-Hyun Han, Icheon-si (KR); Hyang-Keun Yoo, Seongnam-si (KR); and Se-Ho Lee, Yongin-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 12, 2021, as Appl. No. 17/498,849.
Application 17/498,849 is a continuation of application No. 16/713,163, filed on Dec. 13, 2019, granted, now 11,171,178.
Claims priority of application No. 10-2019-0090127 (KR), filed on Jul. 25, 2019.
Prior Publication US 2022/0028931 A1, Jan. 27, 2022
Int. Cl. H10B 63/00 (2023.01); G11C 5/06 (2006.01); G11C 13/00 (2006.01); H10N 70/00 (2023.01)
CPC H10B 63/84 (2023.02) [G11C 5/06 (2013.01); G11C 13/0002 (2013.01); H10N 70/826 (2023.02)] 4 Claims
OG exemplary drawing
 
1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising:
a substrate having a substantially horizontal upper surface;
first to Nth layers (where N is a natural number of two or more) disposed in horizontal layers on the substrate and spaced apart from each other above the substrate in a vertical direction, wherein each of the first to Nth layers includes a plurality of conductive lines;
an insulating layer disposed to fill spaces between the conductive lines vertically;
a hole having sidewalls that extends in the vertical direction through the conductive lines of the first to Nth layers and the insulating layer therebetween;
a variable resistance layer disposed on the sidewalls of the hole; and
a conductive pillar disposed to fill the hole in which the variable resistance layer is formed.