US 11,729,995 B1
Common mode compensation for non-linear polar material 1TnC memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 1, 2021, as Appl. No. 17/516,572.
Application 17/516,572 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 53/30 (2023.01); G11C 11/24 (2006.01); H10B 53/40 (2023.01); G11C 11/404 (2006.01); G11C 11/405 (2006.01)
CPC H10B 53/30 (2023.02) [G11C 11/24 (2013.01); H10B 53/40 (2023.02); G11C 11/404 (2013.01); G11C 11/405 (2013.01)] 20 Claims
OG exemplary drawing
 
15. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes a bit-cell which comprises:
a node;
a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the node and a second terminal coupled to a first plate-line;
a second capacitor comprising the non-linear polar material, the second capacitor having a third terminal coupled to the node and a fourth terminal coupled to a second plate-line;
a transistor coupled to the node and a bit-line, wherein the transistor is controllable by a word-line; and
a third capacitor coupled to the node and a third plate-line, wherein the second capacitor comprises a linear dielectric.