CPC H10B 53/20 (2023.02) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/4045 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H01L 21/02197 (2013.01)] | 20 Claims |
18. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes a differential bit-cell which comprises:
a first bit-cell comprising a first transistor coupled to a first bit-line and controllable by a word-line, wherein the first transistor is coupled to a first capacitor comprising non-linear polar material, wherein the first transistor is coupled to a second capacitor comprising dielectric material, wherein the first capacitor is coupled to a first plate-line, and wherein the second capacitor is coupled to a second plate-line; and
a second bit-cell comprising a second transistor coupled to a second bit-line and controllable by the word-line, wherein the second transistor is coupled to a third capacitor comprising the non-linear polar material, wherein the second transistor is coupled to a fourth capacitor comprising the dielectric material, wherein the third capacitor is coupled to the first plate-line, and wherein the fourth capacitor is coupled to the second plate-line.
|