US 11,729,991 B1
Common mode compensation for non-linear polar material based differential memory bit-cell
Rajeev Kumar Dokania, Beaverton, OR (US); Noriyuki Sato, Hillsboro, OR (US); Tanay Gosavi, Portland, OR (US); Amrita Mathuriya, Portland, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Nov. 1, 2021, as Appl. No. 17/516,587.
Application 17/516,587 is a continuation of application No. 17/516,293, filed on Nov. 1, 2021.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/00 (2006.01); H10B 53/20 (2023.01); G11C 11/22 (2006.01); G11C 11/404 (2006.01); H10B 12/00 (2023.01); H01L 21/02 (2006.01)
CPC H10B 53/20 (2023.02) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/4045 (2013.01); H10B 12/056 (2023.02); H10B 12/36 (2023.02); H01L 21/02197 (2013.01)] 20 Claims
OG exemplary drawing
 
18. A system comprising:
a processor circuitry to execute one or more instructions;
a memory coupled to the processor circuitry; and
a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes a differential bit-cell which comprises:
a first bit-cell comprising a first transistor coupled to a first bit-line and controllable by a word-line, wherein the first transistor is coupled to a first capacitor comprising non-linear polar material, wherein the first transistor is coupled to a second capacitor comprising dielectric material, wherein the first capacitor is coupled to a first plate-line, and wherein the second capacitor is coupled to a second plate-line; and
a second bit-cell comprising a second transistor coupled to a second bit-line and controllable by the word-line, wherein the second transistor is coupled to a third capacitor comprising the non-linear polar material, wherein the second transistor is coupled to a fourth capacitor comprising the dielectric material, wherein the third capacitor is coupled to the first plate-line, and wherein the fourth capacitor is coupled to the second plate-line.