US 11,729,988 B2
Memory device comprising conductive pillars and method of forming the same
Yu-Wei Jiang, Hsinchu (TW); Sheng-Chih Lai, Hsinchu County (TW); Tsuching Yang, Taipei (TW); Hung-Chang Sun, Kaohsiung (TW); and Kuo-Chang Chiang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 27, 2021, as Appl. No. 17/159,179.
Claims priority of provisional application 63/040,538, filed on Jun. 18, 2020.
Prior Publication US 2021/0399016 A1, Dec. 23, 2021
Int. Cl. H10B 51/20 (2023.01); H01L 29/24 (2006.01); H10B 51/10 (2023.01); H10B 51/30 (2023.01)
CPC H10B 51/20 (2023.02) [H01L 29/24 (2013.01); H10B 51/10 (2023.02); H10B 51/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a multi-layer stack, disposed on a substrate and comprising a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction;
a channel layer, penetrating through the plurality of conductive layers and the plurality of dielectric layers;
a memory material layer, disposed between the channel layer and each of the plurality of conductive layers and the plurality of dielectric layers; and
at least three conductive pillars, extending in the first direction, surrounded by the channel layer and the memory material layer, wherein the at least three conductive pillars are electrically connected to conductive lines respectively, and the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.