US 11,729,987 B2
Memory array source/drain electrode structures
Kuo-Chang Chiang, Hsinchu (TW); Hung-Chang Sun, Kaohsiung (TW); Sheng-Chih Lai, Hsinchu (TW); TsuChing Yang, Taipei (TW); and Yu-Wei Jiang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Dec. 11, 2020, as Appl. No. 17/119,409.
Claims priority of provisional application 63/046,002, filed on Jun. 30, 2020.
Prior Publication US 2021/0408045 A1, Dec. 30, 2021
Int. Cl. H10B 51/20 (2023.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); G11C 11/22 (2006.01)
CPC H10B 51/20 (2023.02) [G11C 11/223 (2013.01); H01L 27/1225 (2013.01); H01L 29/66742 (2013.01); H01L 29/7869 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a thin film transistor over a semiconductor substrate, the thin film transistor comprising:
a memory film contacting a word line; and
an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line are each physically separated from the memory film by the OS layer, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6; and
a dielectric material separating the source line and the bit line.