US 11,729,980 B2
3-dimensional NOR memory array architecture and methods for fabrication thereof
Eli Harari, Saratoga, CA (US); Scott Brad Herner, Portland, OR (US); and Wu-Yi Henry Chien, San Jose, CA (US)
Assigned to SunRise Memory Corporation, San Jose, CA (US)
Filed by SunRise Memory Corporation, San Jose, CA (US)
Filed on Mar. 9, 2022, as Appl. No. 17/690,943.
Application 17/690,943 is a continuation of application No. 17/011,836, filed on Sep. 3, 2020, granted, now 11,309,331.
Application 17/011,836 is a continuation of application No. 16/792,790, filed on Feb. 17, 2020, granted, now 10,818,692, issued on Oct. 27, 2020.
Application 16/792,790 is a continuation of application No. 16/012,731, filed on Jun. 19, 2018, granted, now 10,608,011, issued on Mar. 21, 2020.
Claims priority of provisional application 62/550,553, filed on Aug. 25, 2017.
Claims priority of provisional application 62/522,666, filed on Jun. 20, 2017.
Claims priority of provisional application 62/522,661, filed on Jun. 20, 2017.
Claims priority of provisional application 62/522,665, filed on Jun. 20, 2017.
Prior Publication US 2022/0199643 A1, Jun. 23, 2022
Int. Cl. H01L 21/00 (2006.01); H10B 43/27 (2023.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H10B 43/20 (2023.01); H01L 21/311 (2006.01); G11C 16/04 (2006.01)
CPC H10B 43/27 (2023.02) [H01L 21/7682 (2013.01); H01L 21/76802 (2013.01); H01L 23/562 (2013.01); H10B 43/20 (2023.02); G11C 16/0466 (2013.01); H01L 21/31111 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory structure, comprising:
a semiconductor substrate having a substantially planar surface;
a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction substantially parallel the planar surface, wherein each stack of active strips comprises two or more active strips provided one on top of another, with adjacent active strips being isolated from each other by an isolation layer, the active strips being substantially aligned lengthwise with each other along a second direction that is substantially also parallel to the planar surface but orthogonal the first direction, and wherein each active strip comprises a dielectric layer provided between a conductive common source layer and a conductive common drain layer, and a channel layer in contact with both the common source layer and the common drain layer, the dielectric layer, the common source layer and the common drain layer being stacked along a third direction that is substantially normal to the planar surface;
a storage layer; and
a plurality of conductors, serving as gate electrodes, each extending lengthwise along the third direction, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the storage layer and the channel layer, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of storage transistors that are formed out of the common source layer, the common drain layer, the channel layer and their adjacent storage layer and the conductors within the group.