US 11,729,979 B2
Memory device and method for fabricating the memory device
Jin-Ho Bin, Hanam-si (KR); Il-Young Kwon, Seoul (KR); Tae-Hong Gwon, Icheon-si (KR); and Hye-Hyeon Byeon, Pohang-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 24, 2021, as Appl. No. 17/535,244.
Application 17/535,244 is a continuation of application No. 16/710,916, filed on Dec. 11, 2019, granted, now 11,217,602.
Claims priority of application No. 10-2019-0068038 (KR), filed on Jun. 10, 2019.
Prior Publication US 2022/0085069 A1, Mar. 17, 2022
Int. Cl. H10B 43/27 (2023.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 41/35 (2023.01); H10B 43/10 (2023.01); H10B 43/35 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 43/10 (2023.02); H10B 43/35 (2023.02)] 7 Claims
OG exemplary drawing
 
1. A memory device comprising:
an alternating stack of conductive layers and dielectric layers located over a substrate;
a vertical channel structure that penetrates the alternating stack;
a covering blocking layer that surrounds an outer wall of the vertical channel structure; and
a protruding blocking layer that extends from the covering blocking layer and contacts edges of the conductive layers,
wherein each of the conductive layers comprises a round-like edge contacting the protruding blocking layer,
wherein the protruding blocking layer contacts the dielectric layers, and comprises interface portions having cusp shapes and a middle portion between the interface portions, and
wherein each of the interface portions comprises oxide of porous nitride.