US 11,729,972 B2
3D memory devices
Younghwan Son, Hwaseong-si (KR); Seogoo Kang, Seoul (KR); and Jeehoon Han, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 9, 2020, as Appl. No. 16/844,429.
Claims priority of application No. 10-2019-0093370 (KR), filed on Jul. 31, 2019.
Prior Publication US 2021/0036011 A1, Feb. 4, 2021
Int. Cl. H10B 43/27 (2023.01); G11C 8/14 (2006.01); G11C 7/18 (2006.01); H01L 29/423 (2006.01); H01L 29/792 (2006.01); H10B 43/10 (2023.01); H01L 21/28 (2006.01)
CPC H10B 43/27 (2023.02) [G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 29/4234 (2013.01); H01L 29/7926 (2013.01); H10B 43/10 (2023.02); H01L 29/40117 (2019.08)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a channel structure on a substrate and extending in a first direction perpendicular to a top surface of the substrate, the channel structure comprising
a body gate layer extending in the first direction;
a charge storage structure surrounding a sidewall of the body gate layer; and
a channel layer surrounding a sidewall of the charge storage structure, an upper surface of the charge storage structure and an upper surface of the channel layer are at a same level;
a plurality of gate electrodes on the substrate and spaced apart from one another in the first direction on a sidewall of the channel structure; and
a gate insulating layer between each of the plurality of gate electrodes and the channel structure; and
a body gate contact contacting the body gate layer; and
a bit line contact being in electrical contact with the channel layer.