US 11,729,970 B2
Input and digital output mechanisms for analog neural memory in a deep learning artificial neural network
Hieu Van Tran, San Jose, CA (US); Steven Lemke, Boulder Creek, CA (US); Vipin Tiwari, Dublin, CA (US); Nhan Do, Saratoga, CA (US); and Mark Reiten, Alamo, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Dec. 14, 2020, as Appl. No. 17/121,555.
Application 17/121,555 is a continuation of application No. 16/919,697, filed on Jul. 2, 2020.
Application 16/919,697 is a continuation of application No. 16/231,231, filed on Dec. 21, 2018, granted, now 10,741,568.
Claims priority of provisional application 62/746,470, filed on Oct. 16, 2018.
Prior Publication US 2021/0098477 A1, Apr. 1, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 27/11531 (2017.01); G06N 3/08 (2023.01); G11C 16/04 (2006.01); H01L 29/788 (2006.01); H10B 41/42 (2023.01)
CPC H10B 41/42 (2023.02) [G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method of reading a selected non-volatile memory cell, the method comprising:
providing a plurality of input bits to an input circuit;
generating, by the input circuit, one or more input pulses in response to the plurality of input bits, where each value represented by the plurality of input bits results in generation of a different number of input pulses;
applying the input pulses to a terminal of the selected non-volatile memory cell;
receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input pulse in the one or more input pulses; and
summing the plurality of output signals to determine a value stored in the selected non-volatile memory cell.
 
10. A method of reading a selected non-volatile memory cell, the method comprising:
providing a set of input bits to an input circuit;
sequentially applying, by the input circuit, an input signal to a terminal of the selected non-volatile memory cell for each input bit in the set of input bits;
sequentially receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input signal;
sequentially applying, by the output circuit, a binary weight to each output signal based on the binary location of the input bit within the set of input bits to generate a weighted output signal; and
summing, by the output circuit, the weighted output signals to determine a value stored in the selected non-volatile memory cell.