CPC H10B 41/42 (2023.02) [G06N 3/08 (2013.01); G11C 16/0425 (2013.01); H01L 29/7883 (2013.01)] | 16 Claims |
1. A method of reading a selected non-volatile memory cell, the method comprising:
providing a plurality of input bits to an input circuit;
generating, by the input circuit, one or more input pulses in response to the plurality of input bits, where each value represented by the plurality of input bits results in generation of a different number of input pulses;
applying the input pulses to a terminal of the selected non-volatile memory cell;
receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input pulse in the one or more input pulses; and
summing the plurality of output signals to determine a value stored in the selected non-volatile memory cell.
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10. A method of reading a selected non-volatile memory cell, the method comprising:
providing a set of input bits to an input circuit;
sequentially applying, by the input circuit, an input signal to a terminal of the selected non-volatile memory cell for each input bit in the set of input bits;
sequentially receiving, by an output circuit, a plurality of output signals, each output signal received from a column containing the selected non-volatile memory cell in response to an input signal;
sequentially applying, by the output circuit, a binary weight to each output signal based on the binary location of the input bit within the set of input bits to generate a weighted output signal; and
summing, by the output circuit, the weighted output signals to determine a value stored in the selected non-volatile memory cell.
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