US 11,729,965 B2
Capacitor, semiconductor device, and manufacturing method of semiconductor device
Yuichi Sato, Kanagawa (JP); Ryota Hodo, Kanagawa (JP); Yuta Iida, Kanagawa (JP); and Tomoaki Moriwaka, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jun. 27, 2022, as Appl. No. 17/849,854.
Application 17/849,854 is a continuation of application No. 16/478,532, granted, now 11,380,688, previously published as PCT/IB2018/050297, filed on Jan. 18, 2018.
Claims priority of application No. 2017-013142 (JP), filed on Jan. 27, 2017.
Prior Publication US 2022/0359523 A1, Nov. 10, 2022
Int. Cl. H10B 12/00 (2023.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 23/532 (2006.01)
CPC H10B 12/30 (2023.02) [H01L 21/02266 (2013.01); H01L 21/02274 (2013.01); H01L 21/31116 (2013.01); H01L 21/3212 (2013.01); H01L 23/5329 (2013.01); H10B 12/02 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a semiconductor layer;
a first insulator comprising a depressed portion over the semiconductor layer;
a first conductor electrically connected to the semiconductor layer, the first conductor penetrating the first insulator;
a second insulator over the first insulator, the second insulator comprising an opening overlapping with the depressed portion and the first conductor; and
a second conductor in direct contact with the depressed portion, a curved surface of the first conductor, and an inner wall of the opening,
wherein the first conductor penetrates the second insulator, and
wherein the first conductor comprises the curved surface in a portion above a top surface of the first insulator.
 
2. A semiconductor device comprising:
a semiconductor layer;
a first insulator comprising a depressed portion over the semiconductor layer;
a first conductor electrically connected to the semiconductor layer, the first conductor penetrating the first insulator;
a second insulator over the first insulator, the second insulator comprising an opening overlapping with the depressed portion and the first conductor;
a second conductor in direct contact with the depressed portion, a curved surface of the first conductor, and an inner wall of the opening;
a third insulator over the second conductor and in the opening; and
a third conductor over the third insulator,
wherein the third conductor overlaps with the semiconductor layer, and
wherein the first conductor comprises the curved surface in a portion above a top surface of the first insulator.