US 11,729,962 B2
Memory device
Ki Hong Lee, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 3, 2021, as Appl. No. 17/166,437.
Claims priority of application No. 10-2020-0113116 (KR), filed on Sep. 4, 2020.
Prior Publication US 2022/0077151 A1, Mar. 10, 2022
Int. Cl. H01L 27/108 (2006.01); H10B 12/00 (2023.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 49/02 (2006.01)
CPC H10B 12/30 (2023.02) [H01L 28/40 (2013.01); H01L 29/0673 (2013.01); H01L 29/0684 (2013.01); H01L 29/42392 (2013.01); H01L 29/7869 (2013.01); H01L 29/78654 (2013.01); H01L 29/78672 (2013.01); H01L 29/78696 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10B 12/48 (2023.02); H10B 12/482 (2023.02); H10B 12/50 (2023.02); H10B 12/485 (2023.02); H10B 12/488 (2023.02)] 32 Claims
OG exemplary drawing
 
23. A memory cell, comprising:
a substrate;
a bit line vertically oriented from the substrate along a first direction;
at least two nanosheets horizontally oriented from the bit line along a second direction perpendicular to the first direction;
a word line including a surrounding portion surrounding the at least two nanosheets and a first buried portion, and a second buried portion extending from the surrounding portion along the second direction;
a first doped portion horizontally oriented from a first side of the nanosheets, connected to the bit line, and surrounding the first buried portion;
a second doped portion horizontally oriented from a second side of the nano sheets and surrounding the second buried portion; and
a capacitor horizontally oriented from the second doped portion along the second direction.