US 11,729,096 B2
Techniques to support multiple protocols between computer system interconnects
Debendra Das Sharma, Saratoga, CA (US); Michelle C. Jen, Mountain View, CA (US); Mark S. Myers, Portland, OR (US); Don Soltis, Windsor, CO (US); Ramacharan Sundararaman, Hillsboro, OR (US); Stephen R. Van Doren, Portland, OR (US); and Mahesh Wagh, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 2, 2021, as Appl. No. 17/391,557.
Application 17/391,557 is a continuation of application No. 15/639,393, filed on Jun. 30, 2017, granted, now 11,095,556.
Prior Publication US 2021/0399982 A1, Dec. 23, 2021
Int. Cl. H04L 45/52 (2022.01); H04L 69/18 (2022.01); H04L 49/60 (2022.01); H04L 69/323 (2022.01)
CPC H04L 45/52 (2013.01) [H04L 49/60 (2013.01); H04L 69/18 (2013.01); H04L 69/323 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a multi-protocol multiplexer to receive at least one of first information of a first interconnect protocol or second information of a second interconnect protocol, the multi-protocol multiplexer to direct the at least one of the first information or the second information to a physical layer; and
the physical layer coupled to the multi-protocol multiplexer, wherein the physical layer is to receive the first information of the first interconnect protocol and output a packet on a plurality of lanes, the packet comprising a protocol ID and payload information comprising a plurality of flits,
wherein the physical layer is to:
send a sync header on the plurality of lanes;
send the protocol ID in 8-bit chunks on two consecutive lanes of the plurality of lanes, wherein the protocol ID is to be sent prior to the plurality of flits; and
send the plurality of flits on the plurality of lanes.