US 11,728,817 B2
Clock and data recovery devices with fractional-N PLL
Mrunmay Talegaonkar, Laguna Hills, CA (US); Jorge Pernillo, Daly City, CA (US); Junyi Sun, Singapore (SG); Praveen Prabha, Lake Forest, CA (US); Chang-Feng Loi, Singapore (SG); Yu Liao, Longmont, CO (US); Jamal Riani, Fremont, CA (US); Belal Helal, Santa Clara, CA (US); Karthik S. Gopalakrishnan, Cupertino, CA (US); and Aaron Buchwald, Newport Beach, CA (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by Marvell Asia Pte Ltd., Singapore (SG)
Filed on Jan. 3, 2022, as Appl. No. 17/567,588.
Application 17/567,588 is a continuation of application No. 17/013,307, filed on Sep. 4, 2020, granted, now 11,218,156, issued on Jan. 4, 2022.
Application 17/013,307 is a continuation of application No. 16/127,103, filed on Sep. 10, 2018, granted, now 10,804,913, issued on Oct. 13, 2020.
Prior Publication US 2022/0190836 A1, Jun. 16, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H03L 7/197 (2006.01); H04L 7/033 (2006.01); H03L 7/099 (2006.01); H03L 7/087 (2006.01); H03L 7/08 (2006.01)
CPC H03L 7/1976 (2013.01) [H03L 7/087 (2013.01); H03L 7/0807 (2013.01); H03L 7/099 (2013.01); H04L 7/0331 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A clock and data recovery (CDR) device, comprising:
a digital phase detector circuit configured to (i) receive a data signal and an output clock signal, (ii) detect a phase difference between the data signal and the output clock signal, and (iii) generate a phase difference signal based on the detected phase difference; and
a fractional-N phase lock loop (Frac-N PLL) circuit configured to control either one of an output frequency and an output phase of the output clock signal according to a digital frequency control signal that is based on the detected phase difference between the data signal and the output clock signal, the Frac-N PLL circuit being configured to (i) receive the digital frequency control signal and a reference clock signal, the digital frequency control signal being indicative of the phase difference between the data signal and the output clock signal (ii) generate the output clock signal using an oscillator that is controlled in accordance with the digital frequency control signal and the reference clock signal,
wherein the Frac-N PLL circuit comprises a feedforward path circuit that includes a sigma delta modulator configured to generate an oscillator compensation signal based on the digital frequency control signal and a digital gain scaling factor.