US 11,728,432 B2
Cut metal gate in memory macro edge and middle strap
Hsin-Wen Su, Hsinchu (TW); Yu-Kuan Lin, Taipei (TW); Chih-Chuan Yang, Hsinchu (TW); Chang-Ta Yang, Hsinchu (TW); and Shih-Hao Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jun. 21, 2021, as Appl. No. 17/352,587.
Application 17/352,587 is a continuation of application No. 16/441,217, filed on Jun. 14, 2019, granted, now 11,043,595.
Prior Publication US 2021/0313463 A1, Oct. 7, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/76224 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory macro, wherein the memory macro includes:
a first well pick-up (WPU) area oriented lengthwise generally along a first direction; and
memory bit areas adjacent to the first WPU area,
wherein, in the first WPU area, the memory macro includes:
n-type wells and p-type wells arranged alternately along the first direction with well boundaries between the adjacent n-type and p-type wells;
fin active regions extending from the n-type and the p-type wells, wherein the fin active regions are oriented lengthwise generally along a second direction perpendicular to the first direction;
gate structures over the n-type and p-type wells and oriented lengthwise generally along the first direction;
a first dielectric layer disposed at each of the well boundaries, wherein from a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area;
first contact features disposed over and in electrical contact with one of the p-type wells, wherein the first contact features are disposed between the gate structures from a top view; and
second contact features disposed over and in electrical contact with one of the n-type wells, wherein the second contact features are disposed between the gate structures from a top view.