CPC H01L 29/785 (2013.01) [H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/76224 (2013.01)] | 20 Claims |
1. A semiconductor device, comprising:
a memory macro, wherein the memory macro includes:
a first well pick-up (WPU) area oriented lengthwise generally along a first direction; and
memory bit areas adjacent to the first WPU area,
wherein, in the first WPU area, the memory macro includes:
n-type wells and p-type wells arranged alternately along the first direction with well boundaries between the adjacent n-type and p-type wells;
fin active regions extending from the n-type and the p-type wells, wherein the fin active regions are oriented lengthwise generally along a second direction perpendicular to the first direction;
gate structures over the n-type and p-type wells and oriented lengthwise generally along the first direction;
a first dielectric layer disposed at each of the well boundaries, wherein from a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area;
first contact features disposed over and in electrical contact with one of the p-type wells, wherein the first contact features are disposed between the gate structures from a top view; and
second contact features disposed over and in electrical contact with one of the n-type wells, wherein the second contact features are disposed between the gate structures from a top view.
|