US 11,728,409 B2
Semiconductor device
Sun Hye Lee, Yongin-si (KR); Sung Soo Kim, Hwaseong-si (KR); Ik Soo Kim, Yongin-si (KR); Woong Sik Nam, Seoul (KR); and Dong Hyun Roh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 4, 2020, as Appl. No. 17/112,357.
Claims priority of application No. 10-2020-0047996 (KR), filed on Apr. 21, 2020.
Prior Publication US 2021/0328039 A1, Oct. 21, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); B82Y 10/00 (2011.01)
CPC H01L 29/6656 (2013.01) [H01L 29/0673 (2013.01); H01L 29/1033 (2013.01); H01L 29/1079 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); B82Y 10/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
first and second active patterns each extending in a first direction and spaced apart from each other in a second direction that is perpendicular to the first direction;
a field insulating layer disposed between the first active pattern and the second active pattern;
a first gate structure disposed on the first active pattern and extending in the second. direction;
an interlayer insulating layer disposed between the first gate structure and the field insulating layer, the interlayer insulating layer including a first part disposed below the first gate structure; and
a spacer disposed between the first gate structure and the first part of the interlayer insulating layer, wherein an upper surface of the spacer has a height that is greater than a height of lowermost surface of the first gate structure.