US 11,728,354 B2
Electronic device
Takeshi Aoki, Kanagawa (JP); Yoshiyuki Kurokawa, Kanagawa (JP); Takayuki Ikeda, Kanagawa (JP); and Hikaru Tamura, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Aug. 23, 2022, as Appl. No. 17/893,247.
Application 14/990,934 is a division of application No. 13/224,655, filed on Sep. 2, 2011, granted, now 9,252,171, issued on Feb. 2, 2016.
Application 17/893,247 is a continuation of application No. 17/223,248, filed on Apr. 6, 2021, granted, now 11,430,820.
Application 17/223,248 is a continuation of application No. 16/902,124, filed on Jun. 15, 2020, granted, now 11,239,268, issued on Feb. 1, 2022.
Application 16/902,124 is a continuation of application No. 16/161,209, filed on Oct. 16, 2018, granted, now 10,685,992, issued on Jun. 16, 2020.
Application 16/161,209 is a continuation of application No. 14/990,934, filed on Jan. 8, 2016, granted, now 10,109,661, issued on Oct. 23, 2018.
Claims priority of application No. 2010-198928 (JP), filed on Sep. 6, 2010.
Prior Publication US 2022/0406826 A1, Dec. 22, 2022
Int. Cl. H01L 27/146 (2006.01); G09G 3/36 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/14603 (2013.01) [G09G 3/3648 (2013.01); H01L 27/14612 (2013.01); H01L 27/14616 (2013.01); H01L 27/14625 (2013.01); H01L 27/14636 (2013.01); H01L 27/14641 (2013.01); H01L 27/14643 (2013.01); H01L 29/7869 (2013.01); G09G 2354/00 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a photodiode;
a first transistor;
a second transistor; and
a third transistor,
wherein a first electrode of the photodiode is electrically connected to a first wire,
wherein a second electrode of the photodiode is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to a second wire,
wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a third wire,
wherein a gate of the first transistor is electrically connected to a fourth wire,
wherein a gate of the third transistor is electrically connected to a fifth wire,
wherein the first wire is electrically connected to a sixth wire,
wherein the first wire and the sixth wire cross each other, and
wherein the first wire and the fifth wire cross each other.