US 11,728,349 B2
Display device and electronic device including the same
Jun Koyama, Sagamihara (JP); and Shunpei Yamazaki, Setagaya (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Dec. 1, 2021, as Appl. No. 17/539,249.
Application 17/539,249 is a continuation of application No. 16/653,007, filed on Oct. 15, 2019, abandoned.
Application 16/653,007 is a continuation of application No. 15/988,534, filed on May 24, 2018, granted, now 10,840,268, issued on Nov. 17, 2020.
Application 15/988,534 is a continuation of application No. 15/370,034, filed on Dec. 6, 2016, granted, now 9,991,286, issued on Jun. 5, 2018.
Application 15/370,034 is a continuation of application No. 14/507,204, filed on Oct. 6, 2014, granted, now 9,721,971, issued on Aug. 1, 2017.
Application 14/507,204 is a continuation of application No. 13/570,297, filed on Aug. 9, 2012, granted, now 8,866,138, issued on Oct. 21, 2014.
Application 13/570,297 is a continuation of application No. 12/957,517, filed on Dec. 1, 2010, granted, now 8,247,813, issued on Aug. 21, 2012.
Claims priority of application No. 2009-276918 (JP), filed on Dec. 4, 2009.
Prior Publication US 2022/0173129 A1, Jun. 2, 2022
Int. Cl. H01L 21/00 (2006.01); H01L 27/12 (2006.01); G02F 1/1345 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01); G02F 1/1368 (2006.01); G02F 1/1333 (2006.01); G02F 1/1343 (2006.01); G02F 1/1362 (2006.01); G09G 3/3266 (2016.01); G09G 3/3275 (2016.01); G09G 3/36 (2006.01)
CPC H01L 27/1225 (2013.01) [G02F 1/13454 (2013.01); H01L 27/124 (2013.01); H01L 27/1285 (2013.01); H01L 29/045 (2013.01); H01L 29/66742 (2013.01); H01L 29/66969 (2013.01); H01L 29/7869 (2013.01); G02F 1/1368 (2013.01); G02F 1/13452 (2013.01); G02F 1/133345 (2013.01); G02F 1/134309 (2013.01); G02F 1/136286 (2013.01); G02F 2201/123 (2013.01); G09G 3/3266 (2013.01); G09G 3/3275 (2013.01); G09G 3/3677 (2013.01); G09G 3/3688 (2013.01); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2330/023 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a substrate comprising a top surface;
a gate electrode layer over the substrate, and comprising a top surface and a side surface, the side surface having an inclination with respect to the top surface of the substrate;
a first oxide semiconductor layer over the substrate with the gate electrode layer interposed therebetween;
a second oxide semiconductor layer over the first oxide semiconductor layer; and
a gate insulating layer between the gate electrode layer and the first oxide semiconductor layer,
wherein the second oxide semiconductor layer comprises a first region overlapping with the top surface of the gate electrode layer and a second region inclined in response to the inclination of the side surface of the gate electrode layer,
wherein a first crystal in the first region of the second oxide semiconductor layer has a c-axis alignment along a thickness direction of the first region of the second oxide semiconductor layer,
wherein a second crystal in the second region of the second oxide semiconductor layer has a c-axis alignment along a thickness direction of the second region of the second oxide semiconductor layer, and
wherein a direction of a c-axis of the first crystal is different from a direction of a c-axis of the second crystal.