US 11,728,347 B2
Method of manufacturing an integrated circuit device
Weonhong Kim, Suwon-si (KR); Pilkyu Kang, Suwon-si (KR); Yuichiro Sasaki, Suwon-si (KR); Sungkeun Lim, Suwon-si (KR); Yongho Ha, Suwon-si (KR); Sangjin Hyun, Suwon-si (KR); Kughwan Kim, Suwon-si (KR); and Seungha Oh, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 5, 2021, as Appl. No. 17/494,275.
Application 17/494,275 is a division of application No. 16/807,410, filed on Mar. 3, 2020, granted, now 11,177,286.
Claims priority of application No. 10-2019-0059129 (KR), filed on May 20, 2019.
Prior Publication US 2022/0028895 A1, Jan. 27, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/762 (2006.01); H01L 27/02 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/76224 (2013.01); H01L 27/0203 (2013.01); H01L 27/02 (2013.01); H01L 29/78 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method of manufacturing an integrated circuit device, the method comprising:
preparing a semiconductor-on-insulator (SOI) substrate, on which a base substrate layer, an embedded insulation layer, and a semiconductor layer are sequentially stacked;
forming a deep trench that defines at least two element regions, by partially removing the semiconductor layer;
forming a preliminary separation insulation layer to fill the deep trench;
forming a buried rail hole that penetrates through the preliminary separation insulation layer and the semiconductor layer, a buried rail partially filled in a lower portion of the buried rail hole, and a preliminary cover insulation layer filled in an upper portion of the buried rail hole;
exposing the embedded insulation layer by removing the base substrate layer; and
forming a power delivery structure in the embedded insulation layer, the power delivery structure being in contact with the buried rail.