| CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 21/76802 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
a plurality of gate patterns on the substrate, the plurality of gate patterns extending in a first direction and arranged in a second direction intersecting the first direction, the plurality of gate patterns including a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern, the first and second gate patterns being aligned with each other in the first direction, the third and fourth gate patterns being aligned with each other in the first direction, the third gate pattern being spaced apart from the first gate pattern in the second direction, the fourth gate pattern being spaced apart from the second gate pattern in the second direction; and
a separation pattern interposed between the first and second gate patterns and between the third and fourth gate patterns,
wherein the separation pattern includes:
a first separation segment interposed between the first and second gate patterns;
a second separation segment interposed between the third and fourth gate patterns; and
a first protrusion segment connects the first and second separation segments,
wherein a first pitch between the first and second separation segments is substantially the same as a second pitch between the plurality of gate patterns.
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