US 11,728,323 B2
Semiconductor package
Sanguk Kim, Cheonan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 8, 2021, as Appl. No. 17/225,375.
Claims priority of application No. 10-2020-0116095 (KR), filed on Sep. 10, 2020.
Prior Publication US 2022/0077130 A1, Mar. 10, 2022
Int. Cl. H01L 25/18 (2023.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49833 (2013.01); H01L 23/49838 (2013.01); H01L 23/5385 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06515 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16148 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a package substrate;
a first bump and a second bump on a lower surface of the package substrate;
a semiconductor chip on an upper surface of the package substrate;
a first connection pattern and a second connection pattern on the upper surface of the package substrate;
a molding on the upper surface of the package substrate, the molding covering the semiconductor chip;
a warpage control layer on the molding;
an upper insulating layer on the warpage control layer;
a first opening passing through the upper insulating layer and exposing an upper surface of the warpage control layer;
a second opening overlapping the first opening in a top view, the second opening passing through the warpage control layer and exposing the first connection pattern; and
a third opening passing through the upper insulating layer and exposing the second connection pattern.