US 11,728,295 B2
Semiconductor device and method of manufacturing thereof
Tsung-Chieh Hsiao, Shetou Township (TW); Hsiang-Ku Shen, Hsinchu (TW); Yuan-Yang Hsiao, Taipei (TW); Ying-Yao Lai, Hsinchu (TW); and Dian-Hau Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 6, 2021, as Appl. No. 17/367,896.
Claims priority of provisional application 63/166,892, filed on Mar. 26, 2021.
Prior Publication US 2022/0310538 A1, Sep. 29, 2022
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/03 (2013.01) [H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02311 (2013.01); H01L 2224/02313 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01029 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming an opening in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening;
forming one or more liner conductive layers over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer;
forming a main conductive layer over the one or more liner conductive layers;
forming a patterned conductive layer by patterning the main conductive layer and the one or more liner conductive layers using lithography and etching operations; and
forming a cover conductive layer over the patterned conductive layer,
wherein the main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.