US 11,728,294 B2
Capacitor die embedded in package substrate for providing capacitance to surface mounted die
Andrew Collins, Chandler, AZ (US); Sujit Sharan, Chandler, AZ (US); and Jianyong Xie, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 3, 2021, as Appl. No. 17/518,504.
Application 17/518,504 is a continuation of application No. 15/942,092, filed on Mar. 30, 2018, granted, now 11,195,805.
Prior Publication US 2022/0059476 A1, Feb. 24, 2022
Int. Cl. H01L 23/66 (2006.01); H01L 23/522 (2006.01); H01L 23/538 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 21/48 (2006.01); H01L 25/16 (2023.01); H01L 23/48 (2006.01)
CPC H01L 23/66 (2013.01) [H01L 21/4846 (2013.01); H01L 23/5223 (2013.01); H01L 23/5286 (2013.01); H01L 23/5381 (2013.01); H01L 23/5389 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/481 (2013.01); H01L 2223/6666 (2013.01); H01L 2223/6672 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a package substrate;
a capacitor die embedded in the package substrate, wherein the capacitor die is a single-sided capacitor die;
a surface mount die over the capacitor die, the surface mount die comprising a plurality of surface mount die interconnection structures facing the capacitor die;
a plurality of substrate vias between the capacitor die and the surface mount die; and
a short and direct connection coupling one of the plurality of surface mount die interconnection structures to the capacitor die, wherein the one of the plurality of surface mount die interconnection structures is vertically over the capacitor die.