US 11,728,286 B2
Semiconductor structure
Zhuo Cheng, Beijing (CN); and Xiaodong Wang, Beijing (CN)
Assigned to Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed by Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai (CN); and Semiconductor Manufacturing International (Beijing) Corporation, Beijing (CN)
Filed on Sep. 21, 2021, as Appl. No. 17/448,255.
Application 17/448,255 is a division of application No. 16/703,112, filed on Dec. 4, 2019, granted, now 11,171,093.
Claims priority of application No. 201910026202.6 (CN), filed on Jan. 11, 2019.
Prior Publication US 2022/0005769 A1, Jan. 6, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/78 (2013.01)] 9 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a wafer having a functional region and a non-functional region surrounding the functional region;
a first dielectric layer formed on the wafer;
a first opening formed in the first dielectric layer on the non-function region of the wafer; and
a first connection layer formed in the first opening,
wherein the first connection layer closes a top portion of the first opening and a first void is formed in the first connection layer in the first opening.