US 11,728,258 B2
Electroless metal-defined thin pad first level interconnects for lithographically defined vias
Aleksandar Aleksov, Chandler, AZ (US); Veronica Strong, Chandler, AZ (US); Kristof Darmawikarta, Chandler, AZ (US); and Arnab Sarkar, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by INTEL CORPORATION, Santa Clara, CA (US)
Filed on Nov. 29, 2021, as Appl. No. 17/536,711.
Application 17/536,711 is a division of application No. 16/641,219, granted, now 11,257,745, previously published as PCT/US2017/054638, filed on Sep. 29, 2017.
Prior Publication US 2022/0084927 A1, Mar. 17, 2022
Int. Cl. H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 3/02 (2006.01); H05K 3/06 (2006.01); H05K 3/07 (2006.01); H05K 3/10 (2006.01); H01L 21/00 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H05K 1/11 (2006.01); H05K 3/18 (2006.01)
CPC H01L 23/49827 (2013.01) [H01L 21/486 (2013.01); H01L 23/49866 (2013.01); H05K 1/113 (2013.01); H05K 3/184 (2013.01); H05K 2201/0379 (2013.01); H05K 2203/0565 (2013.01)] 6 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) package substrate, comprising:
a metal via extending to a top surface of a dielectric layer; and
a bond pad stack in contact with the metal via, the bond pad stack comprising a plurality of collocated layers, the collocated layers of the bond pad stack comprising:
a first layer comprising a reduced noble metal, a first portion of the reduced noble metal in contact with the metal via and a second portion of the reduced noble metal extending laterally from the metal via over the dielectric layer adjacent to the metal via, wherein a top of the metal via immediately adjacent the first portion of the reduced noble metal comprises oxidized metal; and
a second layer on the first layer, the second layer comprising a second metal.