CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 25/18 (2013.01)] | 11 Claims |
1. A semiconductor package comprising:
a package substrate;
an interposer mounted on the package substrate; and
a semiconductor chip mounted on the interposer,
wherein the interposer comprises
a base layer including a first surface and a second surface opposite the first surface,
a redistribution structure on the first surface of the base layer, configured to mount the semiconductor chip and including a conductive redistribution pattern,
a first lower protection layer on the second surface of the base layer,
a lower conductive pad on the first lower protection layer,
a through electrode passing through the base layer and the first lower protection layer to electrically connect the conductive redistribution pattern to the lower conductive pad,
a second lower protection layer on the first lower protection layer and contacting at least a portion of the lower conductive pad, and
an indentation formed in an outer edge region of the interposer to provide a continuous sidewall extending through the second lower protection layer and through at least a portion of the first lower protection layer,
wherein the continuous sidewall includes a second curvilinear sidewall extending entirely through the second lower protection layer, and a first curvilinear sidewall extending through the at least a portion of the first lower protection layer, and the continuous sidewall is smooth without discontinuous transitions, and
wherein the continuous sidewall further includes a linear sidewall extending within the indentation from the first curvilinear sidewall to an outer wall of the interposer.
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