US 11,728,249 B2
Semiconductor package and method
Wei-Yu Chen, New Taipei (TW); An-Jhih Su, Taoyuan (TW); Der-Chyang Yeh, Hsinchu (TW); Li-Hsien Huang, Zhubei (TW); and Ming Shih Yeh, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 12, 2021, as Appl. No. 17/373,063.
Application 16/588,345 is a division of application No. 15/907,474, filed on Feb. 28, 2018, granted, now 10,529,650, issued on Jan. 7, 2020.
Application 17/373,063 is a continuation of application No. 16/588,345, filed on Sep. 30, 2019, granted, now 11,062,978.
Claims priority of provisional application 62/586,431, filed on Nov. 15, 2017.
Prior Publication US 2021/0343626 A1, Nov. 4, 2021
Int. Cl. H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 25/10 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01)
CPC H01L 23/485 (2013.01) [H01L 21/4857 (2013.01); H01L 21/4867 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5389 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/022 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/0508 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/214 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/97 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
an integrated circuit die;
a first dielectric layer over the integrated circuit die;
an under bump metallurgy extending through the first dielectric layer, the under bump metallurgy connected to the integrated circuit die;
a second dielectric layer over the under bump metallurgy and the first dielectric layer;
a conductive ring sealing an interface of the second dielectric layer and the under bump metallurgy, the conductive ring comprising a first conductive material;
a conductive connector extending through the conductive ring, the conductive connector connected to the under bump metallurgy, the first conductive material of the conductive ring extending between the conductive connector and the second dielectric layer;
a first intermetallic compound at an interface of the conductive connector and the under bump metallurgy; and
a second intermetallic compound at an interface of the conductive connector and the conductive ring, the first intermetallic compound and the second intermetallic compound being different compounds.