US 11,728,245 B2
Semiconductor device and semiconductor package including penetration via structure
Jubin Seo, Seongnam-si (KR); Kwangjin Moon, Hwaseong-si (KR); Kunsang Park, Hwaseong-si (KR); Myungjoo Park, Pohang-si (KR); Sujeong Park, Hwaseong-si (KR); and Jaewon Hwang, Seongnam-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on May 11, 2021, as Appl. No. 17/316,970.
Claims priority of application No. 10-2020-0096758 (KR), filed on Aug. 3, 2020.
Prior Publication US 2022/0037236 A1, Feb. 3, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/5286 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 23/53209 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/08146 (2013.01); H01L 2224/08147 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16147 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16237 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06544 (2013.01); H01L 2225/06548 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1434 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a semiconductor substrate having a first surface and a second surface, which are opposite to each other;
an active pattern protruding from the first surface of the semiconductor substrate, the active pattern including a source/drain region;
a power rail electrically connected to the source/drain region;
a power delivery network disposed on the second surface of the semiconductor substrate;
a device isolation layer disposed on the first surface of the semiconductor substrate and covering a side surface of the active pattern,
wherein the power rail is buried in the device isolation layer; and
a penetration via structure penetrating the semiconductor substrate and electrically connected to the power rail and the power delivery network,
wherein the penetration via structure comprises:
a first conductive pattern electrically connected to the power rail; and
a second conductive pattern electrically connected to the power delivery network,
wherein the first conductive pattern comprises a material different from the second conductive pattern.